1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a semiconductor device having a field insulator and a channel stop for device isolation.
2. Description of the Prior Art
FIG. 1B is a partial cross-section of a memory cell array of a conventional Dynamic Random Access Memory (DRAM) in which each cell has the stacked-capacitor structure, and FIG. 1A is a partial cross-section of the cell shown in FIG. 1B to explain its fabrication process. Here, only the storage node side of the memory cell is shown for the sake of simplification of illustration.
In FIG. 1B, a patterned field oxide 26 for device isolation is formed on the surface of a p-type silicon substrate 21, and a p.sup.+ -type diffusion layer 25 with a high impurity concentration serving as a channel stop is formed just below the field oxide 26 in the substrate 21.
Within each active region formed by the field oxide 26, a metal-oxide-semiconductor (MOS) transistor is formed. The MOS transistor is composed of a gate electrode 28 formed on a gate oxide 27, an n-type diffusion layer 29 and an n-type diffusion layer (not shown) in the same active region, both of the diffusion layers forming a pair of source/drain regions. A patterned polysilicon film serving as the gate electrodes 28 is also serves as word lines 28a on the field oxide 26. As shown FIG. 1B, the n-type diffusion layer 29 is directly contacted with the p.sup.+ -type diffusion layer 25 as the channel stop in the substrate 21.
The surface of the gate electrode 28 and the exposed surfaces of the gate oxide 27 and the field oxide 26 are covered with an interlayer insulator film 30, and on the interlayer insulator film 30, a lower electrode 31 forming an electric charge storage capacitor is formed. The lower electrode 31 has its lower end in contact with the surface of the n-type diffusion layer 29 through a contact hole 35 in the interlayer insulator film 30. Thus, the lower electrode 31 is electrically connected to the n-type diffusion layer 29.
The entire surface of the lower electrode 31 is covered with a dielectric 32 forming the storage capacitor. The surface of the dielectric 32 and the exposed surface of the interlayer insulator film 30 are covered with a common upper electrode 33 forming the respective storage capacitors. The surface of the upper electrode 33 is covered with a passivation layer (not shown).
The conventional DRAM having the above-mentioned configuration is fabricated as follows:
First, a silicon dioxide film 22 and a silicon nitride film 23 are formed on the surface of the p-type silicon substrate 21 in this order and then, a photoresist film 24 is formed on the silicon nitride film 23. After the photoresist film 24 is patterned to the predetermined shape, the silicon nitride film 23 and the silicon dioxide film 22 are patterned by using the photoresist film 24 as a mask, which at this stage is shown in FIG. 1A.
Next, without removing the photoresist film 24, boron ions are selectively implanted into the substrate 21 at an acceleration energy of 100 keV with a dose of 1.times.10.sup.13 /cm.sup.2. Thus the p.sup.+ -type diffusion layer 25 as the channel stop is formed, as shown in FIG. 1A. Subsequently, the photoresist film 24 is removed.
A silicon dioxide film for the field oxide 26 is formed over the entirety of the substrate 21 by a wet thermal oxidation method, and then the silicon nitride film 23 and the silicon dioxide film 22 are removed by etching. Thus, the silicon dioxide film is selectively left on an isolation region of the substrate 21, in which the field oxide 26 is in contact with the surface of the substrate 21, resulting in the patterned field oxide 26. The active regions are formed by the field oxide 26 thus patterned. After the gate oxide 27 is formed on the surface of each of the active regions, a phosphorus-doped polysilicon film is formed on the gate oxides 27 and the field oxide 26. The polysilicon film is then patterned to form the gate electrodes 28 and the word lines connected to each other. N-type dopant ions are selectively implanted into the substrate 21 through the gate oxides 27 using the field oxide 26 and the gate electrodes 28 as a mask thereby to form the n-type diffusion layers 29. Thus, a pair of the source/drain regions made of the n-type diffusion layers 29 is formed in each active region. The n-type diffusion layer 29 can be formed by the following three ways. By a first way, an n.sup.30 -type diffusion layer is formed by an ion-implantation process at a high level dose. By a second way, an n-type diffusion layer with the Lightly Doped Drain (LDD) structure is formed by using a side wall oxide. By a third way, an n.sup.- -type diffusion layer is formed by an ion-implantation process at a low level dose and then, an n.sup.+ -type diffusion layer is formed in the n.sup.- -type diffusion layer in contacting with the lower electrode 31 of the capacitor through the contact hole 35 of the interlayer insulator film 30.
Next, the interlayer insulator film 30 is deposited on the field oxides 26, the gate oxides 27 and the gate electrodes 28 and then, the contact holes 35 are formed in the interlayer insulator film 30 by photolithography and etching processes. As a result, the surfaces of the n-type diffusion layers 29 are partially exposed.
A polysilicon film is deposited on the interlayer insulator film 30 and patterned to form the lower electrodes 31, each of which is in contact with each n-type diffusion layer 29 through each contact hole 35.
A dielectric film is formed on the surfaces of the lower electrodes 31 and an exposed surface of the interlayer insulator film 30 by a thermal oxidation or a Chemical Vapor Deposition (CVD) method, and patterned to form the dielectric 32. Then, a polysilicon film is deposited on the dielectric 32 and the interlayer insulator film 30, and patterned to form the common upper electrode 33. The surface of the upper electrode 33 is covered with the passivation film (not shown). Thus, the conventional DRAM is obtained.
With the memory cell of the conventional DRAM, the p.sup.+ -type diffusion layer 25 as the channel stop is formed by an ion-implantation process of many dopants, so that it usually contains many defects. Besides, the p.sup.+ -type diffusion layer 25 is directly contacted with the n-type diffusion layer 29 as the source/drain region in the substrate 21. Therefore, a large leakage current can easily flow through the p-n junction formed by the p.sup.+ -diffusion layer 25 and the n-type diffusion layer 29. Accordingly, the electric charges stored in the storage capacitor are remarkably reduced and as a result, there arise some problems such as reversal of data. This means that it is difficult to ensure to storing the electric charge which is necessary for the normal operation of the memory in the capacitor.
If the impurity concentration of the p.sup.+ -type diffusion layer 25 is reduced, the leakage current flowing through the p-n junction can be reduced, however, the layer 25 does not function as a channel stop sufficiently. As a result, there arises another problem that a leakage current flowing through a parasitic MOS transistor is increased.